1. Field of Invention
This invention relates to semiconductor device packages and more particularly to device packages having signal traces connecting input/output (I/O) pads of an integrated circuit to device package terminals.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit (i.e., "chip") is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device packages are typically arranged about the periphery of the package. The I/O pads of the chip are electrically connected to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead coplanarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Grid array semiconductor device packages have terminals arranged in a two-dimensional array across an underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and handheld communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array ("BGA") device package. A BGA device includes a chip mounted upon a larger substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). The substrate includes two sets of bonding pads: a first set adjacent to the chip and a second set arranged in a two-dimensional array across the underside surface of the device package. Members of the second set of bonding pads function as device package terminals, and are coated with solder. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. The I/O pads of the chip are typically connected to corresponding members of the first set of bonding pads. Many BGA device packages have die areas dimensioned to receive integrated circuit chips and use established wire bonding techniques to electrically connect the I/O pads of the chips to corresponding flat metal "bonding fingers" adjacent to the die areas. During wire bonding, the I/O pads of the chip are electrically connected to corresponding bonding fingers by fine metal bonding wires. The substrate includes one or more layers of signal lines (i.e., signal traces or interconnects) which connect bonding fingers to corresponding members of the second set of bonding pads. During PCB assembly, the solder balls are placed in physical contact with corresponding bonding pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the bonding pads on the underside of the chip are electrically and mechanically coupled to the bonding pads of the PCB.
The controlled collapse chip connection ("C4") is a well known alternate method of attaching an integrated circuit chip directly to a device package substrate, and is commonly referred to as the "flip chip" method. In preparation for C4 attachment, the I/O pads of the chip are arranged in a two-dimensional array upon an underside of the chip, and a corresponding set of bonding pads are formed upon an upper surface of the device package substrate. A solder bump is formed upon each of the I/O pads of the chip. During C4 attachment of the chip to the device package substrate, the solder bumps are placed in physical contact with the bonding pads of the device package substrate. The solder bumps are then heated long enough for the solder to flow. When the solder cools, the I/O pads of the chip are electrically and mechanically coupled to the bonding pads of the device package substrate. After the chip is attached to the device package substrate, the region between the chip and the device package substrate is filled with an "underfill" material which encapsulates the C4 connections and provides other mechanical advantages.
When the propagation delays of signals along the lengths of semiconductor device package signal traces exceed about one-quarter of the signal rise times, the signal traces begin to behave like transmission lines. The distances between conductors and the electrical properties of the dielectric material providing isolation become major factors in determining the impedances of the signal paths. Impedance changes along the lengths of the signal paths cause signal reflections at high frequencies which may in turn cause data transmission errors. Reliable operation of packaged semiconductor devices at high frequencies (i.e., at signal frequencies where propagation delays of signals along the lengths of the signal traces are greater than about one-quarter of the signal rise times) thus requires signal traces having uniform impedances.
It would be beneficial to have a semiconductor device package having signal traces which present uniform impedances along their entire lengths. Such a semiconductor device package would substantially reduce signal reflections at high frequencies along with resultant data transmission errors, thereby improving the high frequency performance of the semiconductor device package.